1. Field of the Invention
The present invention relates to a semiconductor chip and a semiconductor wafer having power supply pads for a probe test.
2. Description of the Related Art
FIG. 1 is a flow chart illustrating a flow for a typical semiconductor chip testing to be performed to check whether the semiconductor chip operates correctly (such a test is also called as a "device testing").
In a normal test of a semiconductor chip, an operational test 20 (referred to as "a wafer test" hereinafter) for a semiconductor chip sample in a wafer state is first performed and, then, a first judgment step 30 is performed based on a result thereof. A sample judged not to have specified functions is judged as a reject or a failed sample 80 and excluded from further tests conducted later.
Next a packaging step 40 where the sample which passed the judgment step 30 based on the wafer test 20 is performed and, then, an operational test 50 (referred to as "a package test" hereinafter) for the sample in a package state is conducted. Then a second judgment step 60 is conducted based on a result thereof, thereby selecting a final good sample 70.
In the wafer test 20 mentioned above, a needle probe (hereinafter, it may be simply referred to as the "probe") is generally brought into contact with a pad formed on the semiconductor chip to apply test signals or to supply power. The operation of a circuit in response to the applied signal is then measured so as to judge whether the circuit works correctly or not. An operational test utilizing those needle probes mentioned above are referred to as "a probe test".
Accompanied by recent capability of fabricating a submicron configuration in a large scale integration in manufacturing processes of semiconductor chips, manufacture of a submicron, large scale and high speed high pin count chip is becoming possible, which operates faster, has higher functions, and is equipped with more signal pins than a conventional one.
In an operation of such a high speed high pin count chip, potentials at a number of signal pins vary simultaneously at high rate of speed and, therefore, a peak value of current flowing during operation becomes large. A large peak current causes noises in a signal line and/or a power source, resulting in adverse effects on measurement results at the probe test.
On the other hand, when the size of a semiconductor chip becomes large, the length of the wiring which is required during the probe test necessarily gets long. However, such increase in the wiring length, particularly the increase in the power supply wiring length, increases the impedance of the wiring, that is, the resistance component R or the self-inductance component L. Of these, the increase in the resistance component R brings about the occurrence of undesired Joule heating as well as decrease in the voltage supplied from a power source. On the other hand, the increase in the self-inductance component L of the wiring makes the high speed operation of a circuit difficult, resulting in hindering the reduction of time necessary for the probe test, for the following reason.
When a number of signal output pins simultaneously make transition from a high level output to a low level output, or from the low level output to the high level output, a large current flows into a grounding line of a semiconductor chip at the moment of the transition, and the potential of the grounding line rises. Due to this momentary current change (di/dt) and the self-inductance component L of the wiring, an induced voltage component which is determined as -L.multidot.(di/dt) occurs in the wiring and the voltage level fluctuates. This phenomenon is known as the ground bounce phenomenon.
FIG. 12B shows an exemplary waveform observed in a circuit shown in FIG. 12A, including a voltage fluctuation caused by the ground bounce phenomenon. When a potential at an output pin changes from a high level (3V) to a low level (0V), or from the low level (0V) to the high level (3V), a voltage fluctuation appears in an output voltage waveform Vo due to the ground bounce phenomenon as explained above. At this time, an input threshold level fluctuates at an input pin. Furthermore, at an output pin at which a output potential of a constant level is supposed to be maintained by being kept supplied with a constant input potential, a fluctuation is observed in the constant output voltage.
For example, FIG. 12C shows a voltage fluctuation observed at an output pin at which a potential of a constant low level (for example, at 0 V) is output in response to an input voltage of a high level (for example, at 3 V). FIG. 12D, on the other hand, shows a voltage fluctuation observed at an output pin at which a potential of a constant high level (3V) is output in response to an input voltage of a low level (0V). These voltage fluctuations in the output voltage are observed as ringing.
A logic value from an output of a circuit on the semiconductor chip during a period of the occurrence of the ground bounce phenomenon is an error-including output value in a sense that the voltage level thereof includes a fluctuating voltage component due to the ground bounce phenomenon. Therefore, it is necessary to wait to make sampling of a logic value to be output until the ground bounce phenomenon subsides and the voltage level of the output signal returns to a normal value. As a result, high speed operation of the semiconductor chip is hindered.
A needle probe used in a probe test of a semiconductor chip is made of metals such as, for example, tungsten, and has a needle-like shape. However, in a case that the wafer test 20 is conducted using a conventional needle probe made of tungsten, the length of the wiring connected for the test becomes longer compared to the case of the package test 50. As a result, the wiring impedance becomes large and the adverse effect of the above mentioned ground bounce phenomenon largely appears. In order to avoid the influence thereof, it is necessary to sufficiently reduce the test frequency in the wafer test 20 compared to the package test 50, and this poses a problem in view of the efficiency of the test. In other words, in the conventional technique, it is difficult to conduct a test at the maximum operation frequency of the semiconductor chip in the wafer test 20.
In order to solve this problem, it has been attempted to reduce the wiring impedance in the wafer test 20 to as low as the wiring impedance in the package test 50 by sufficiently reducing the impedance of the needle probe used in the test.
The simplest solution is to reduce a resistance component and an inductance component by modifying the shape of the needle probe, for example, with providing an increased cross-section thereof. However, a needle probe having such a large cross-section is disadvantageous in a case where the circuit formed in a semiconductor chip becomes highly integrated and a number of pads are densely formed within a small area. Therefore, this solution is not very effective in view of practicality.
As another solution, the use of a membrane probe card instead of a conventional metal needle probe can be cited. The membrane probe is such that a wiring pattern made of materials such as copper, nickel, gold or the like is formed on a thin insulative base member made of materials such as polyimide, glass epoxy, or the like, and a bump made of copper, gold, solder or the like is provided at the tip portion of the wiring pattern so as to be used as a probe. However, the cost of manufacturing the membrane probe card is much higher compared to the conventional tungsten needle probe and it cannot be perceived as having sufficient practicality.
In regard to those points mentioned above, concerning an operational test of a semiconductor chip, it is not possible in any conventional technique to confirm in the wafer test 20, for example, whether or not the operation of the semiconductor chip is normal at the prescribed maximum operation frequency by raising the test frequency, but it is done in the package test 50 which is conducted after the semiconductor chip is mounted on a package through the packaging step 40. Although a semiconductor chip which does not exhibit a prescribed function at the prescribed maximum operation frequency is ultimately rejected as a failed sample, those semiconductor chips which are unsatisfactory in terms of operation speed and to be ultimately rejected as a failed sample could be mounted on the package since it is difficult to conduct a test for such rejection in the wafer test as mentioned above. This introduces a reduction in the efficiency of the operational test and, moreover, a rise in the total manufacturing cost of the semiconductor chips.
Furthermore, recently in response to the need for miniaturizing a variety of electric-electronic devices including semiconductor chips, there has been a growing number of examples of usage differing from a conventional example in which one semiconductor chip is mounted on a package. One of them is an example in which a bare chip cut out of a semiconductor wafer with no further processing is directly mounted on a print circuit board included in an electronic-electrical device without mounting on a package. Alternatively, examples of adopting a multi-chip module (MCM) in which a plurality of semiconductor chips (bare chips) are mounted on a package with wiring substrate are increasing.
Under these circumstances, it is becoming necessary for a semiconductor manufacturer to sort good samples from failed samples by conducting an operational test ("at speed test") on a bare chip at the maximum operation frequency in order to ensure the performance of semiconductor chips to be supplied. In the MCM, when one of a plurality of bare chips which are put in a package is a failed sample, the MCM itself becomes a failed sample which does not function normally, thereby resulting in a reduction of the production yield. Therefore, not only in a case where the bare chip is used without mounting on a package but also in a case of the MCM, it is necessary to conduct a probe test at a high frequency efficiently and with low cost on a semiconductor chip or a bare chip in a wafer state.